Direct digital synthesizers (DDS) include a phase accumulator, a phase-to-amplitude converter, and a digital-to-analog converter (DAC). In high-speed applications, these functional blocks are generally clocked with pipeline registers internal to each block. The phase-to-amplitude converter can be implemented by various techniques, including using a read only memory (ROM), logic gates, or by a combination of logic gates and a sine-weighted DAC. ROMs, however, are typically not used in high-speed DDS circuits because propagation delays in the ROM circuit make it either impossible to pipeline at high-speed, or are too costly to pipeline in terms of power consumption. As such, instead of a ROM, high-speed DDS circuits typically implement the phase-to-amplitude converter as a combination of logic gates and a sine-weighted DAC. Such conventional approaches suffer from limited spurious-free dynamic range (SFDR), typically in the range of 30 dBc to 40 dBc (i.e., with respect to carrier frequency amplitude) at best.